.Layered Tunnel Barriers
The goal of my research project is to improve the speed of typical nonvolatile floating gate memories by integrating a layered tunnel barrier in place of a homogeneous SiO2 barrier to improve both the speed and retention time of the device.
Here is a schematic of a floating gate memory device (used in your cell phones and digital cameras):
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In this type of device, a voltage is applied to the control gate and also between the source and drain. At a particular threshold voltage electrons will start to tunnel from the channel (region of electron flow between the source and drain) to the floating gate. When all voltages are removed, charge will "permanently" be stored on the floating gate.
The type of tunneling that takes place during the charging process is called Fowler-Nordheim tunneling and it is an inherently slow process. With a thinner tunnel barrier, one could increase the program/erase speed of the device, but the retention time of the device would be decreased simultaneously. On the other hand, by making a thicker tunnel barrier, a greater retention time could be achieved, but program/erase speeds would be sacrificed. Clearly, with this type of homogeneous barrier, there are two extremes to consider.
In my research, I am working to integrate a tunnel barrier that consists of layered dielectric materials with carefully chosen band offsets to simultaneously increase the speed and retention time of a floating gate memory device.
In the following figure, three conduction band diagrams are shown. The outer flat lines represent the conduction band of silicon and the upper ones represent the conduction band of other dielectric materials. The purple dotted line is an approximation of the effective band offset when a voltage V is applied.
In (a), a homogeneous or "square" barrier is represented. When a voltage is applied, electrons travel through an effective triangular barrier. This type of tunneling is defined as Fowler-Nordheim tunneling and is slow, as was mentioned earlier.
In (b), a perfectly graded triangular barrier is drawn. In this case, when a voltage is applied, the overall barrier height that the electrons see is shorter than when the voltage is removed. This allows for fast program and erase speeds as well as longer retention times (the taller barrier height is restored after voltages are removed). However, it isn't possible to make such graded barriers that are compatible with silicon due to industry's inability to deposit high-quality materials with graded compositions.
In (c), a layered dielectric barrier is shown. It was suggested by Konstantin Likharev (K. K. Likharev, Appl. Phys. Lett. 73 (15), 12 October 1998) that the advantage of graded dielectric barriers could be emulated by layering dielectric materials. By choosing materials with appropriately varying band offsets and dielectric constants, we can make silicon compatible tunnel barriers that improve both the program and erase speed of current floating gate memory devices without sacrificing the retention time.
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For more detailed information and simulations we have done to examine the properties of these dielectric barriers, please download my Journal of Applied Physics paper. If you would like to read about our internal photoemission technique for measuring the band-offsets of high-k dielectric materials, please download our recent Applied Physics Letters paper.
In recent months, I have done extensive materials and electrical characterization of my homogeneous and layered barriers in a capacitor type structure. Currently, I am working hard to determine the band offsets of our materials directly by internal photoemission. This will give us a much better understanding of our previously collected experimental data. Published experimental data is still forthcoming, but in the meantime, you can check out a recent presentation I gave at the Fall 2002 Materials Research Society meeting in Boston.